Cadence unveils first analogue IC design-for-reliability solution

Source:Neil Tyler
2018/05/11
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Cadence Design Systems has introduced the Legato Reliability Solution, the industry’s first software product that looks to address the challenges associated with designing high-reliability analogue and mixed-signal integrated circuits (ICs).

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Whether for automotive, medical, industrial, and aerospace and defence applications, the Legato Reliability Solution is able to provide analogue designers with a range of new tools to better manage their design’s reliability throughout the entire lifecycle, from initial test through active life through aging.

Based on Cadence’s Spectre Accelerated Parallel Simulator and the Virtuoso custom IC design platform, Legato integrates capabilities into an intuitive cockpit to address the reliability concerns of the three phases of the product lifecycle, these include:

Analogue defect analysis accelerates analogue defect simulation by up to 100X, reducing test cost and eliminating test escapes, the main source of early failure in IC designs.

Cadence has introduced a simulation engine to enable a new test methodology for analogue ICs. Called defect-oriented testing, it expands the capabilities of test far beyond what is traditionally achieved by just performing functional and parametric tests.

Defect-oriented testing allows designers to evaluate the ability to eliminate die with manufacturing defects and resulting test escapes that cause field failures. It can also be used to optimise wafer test, reducing the number of tests required to achieve the target defect coverage by eliminating over-testing and potentially reducing the number of tests up to 30 percent.

Customer experience with the tool indicates that it accelerates defect simulation by more than 100X.

Electro-thermal analysis avoids premature failures due to thermal overstress during the product’s useful life.

Cadence has introduced a dynamic electro-thermal simulation engine. For automotive designers, for example, actual usage results in significant temperature rise during normal operation due to on-chip losses and power dissipated in the switches. In addition, these components need to operate in hostile environments under the hood of an automobile.

The combination of high-power dissipation in a high-temperature environment can result in thermal overstress that can result in failure during normal operation. Dynamic electro-thermal simulation will allow designers to simulate the on-chip temperature rise and validate the operation of over temperature protection circuits.

Advanced aging analysis enables accurate prediction of product wear-out by analyzing aging acceleration due to temperature and process variation.

With existing technologies, like RelXpert and AgeMOS, to analyse the device degradation due to electrical stress, Cadence has sought to enhance aging analysis and Legato will now include the effects that accelerate device wear-out including temperature and process variation.

Legato will also provide a new aging model for device degradation in advanced nodes with FinFET transistors.

“Designing the chips to meet requirements across the entire product lifecycle has become a huge challenge,” said Tom Beckley, Cadence senior vice president and general manager, custom IC and PCB Group. “Designers are faced with the challenge of designing across the entire lifecycle, including eliminating the test escapes that become field failures early in the life cycle, preventing thermal overstress from operating in extreme conditions like under the hood of a car, and designing for 15 years or more of operating lifetime. Our new Legato Reliability solution enables designers to answer these critical questions much earlier in the design process.”


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