Rambus Adds Security to RISC-V

发布时间：2017-08-22 00:00
作者：Ameya360
来源： Rick Merritt
阅读量：1109

　　Startup SiFive announced a new program providing third-party intellectual property blocks for its RISC-V processors. Its first partnership is for security hardware from Rambus.

　　Rambus will provide a crypto core optimized to connect to its IoT device management services and run on the SiFive Freedom chips. The Rambus core enables a secure connection, attestation and device monitoring, said Martin Scott, general manager of Rambus’s security group.

　　The core is the first member of what SiFive calls DesignShare. “SiFive welcomes everybody to join DesignShare — Rambus is the first of many partners we will be announcing soon,” said Jack Kang, vice president of product and business development at the startup.

　　The program aims to deliver IP “at a low or reduced up front cost,” he said. The blocks will not necessarily be based on open source code.

　　SiFive officially launched in May its first two cores available on its Web site. Although the RISC-V instruction set is open source, the cores require a one-time licensing fee. SiFive does not charge per-unit royalties.

　　SiFive CTO and co-founder Yunsup Lee will give a talk at Hot Chips this week about the company’s products first announced in 2016 as well as the Rambus partnership.

　　Earlier this month, SiFive named industry veteran Naveed Sherwani its CEO. Sherwani has helped found nine startups to date including Open Silicon and Brite Semiconductor. He also helped pioneer Intel’s move to a more open EDA platform for its first ASIC service.

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