Leti Tweaks SRAM to Improve SoC Memory

　　A recent breakthrough by Leti has demonstrated improvements to system-on-chip (SoC) memories, including SRAM.

　　The research institute CEA Tech outlined the results of its research at IEDM 2017 in early December and reported in a paper titled “Advanced Memory Solutions for Emerging Circuits and Systems." The research includes reconfiguring SRAM into content-addressable memory (CAM), improving non-volatile crossbar memories and using advanced tunnel field-effect transistors (TFET).

　　The Leti researchers also presented a high-density SRAM bitcell on its CoolCube 3D platform, which reduces the area required for memory by 30 percent, while maintaining full device functionality. In an interview with EE Times, Bastien Giraud, one of the paper's authors, said the breakthrough provides a path to reducing the major memory bottleneck in more complex SoCs, where up to 90 percent of the SoC area might be taken by SRAM.

　　Memories circuits in SoCs are meeting several technological challenges that need to be addressed, said Giraud. “Among all these challenges, the densest bitcell area associated with a sufficient yield represents a compulsory starting point to build the memory macrocell," he said. “Significant efforts have to be spent on the full memory circuit to enhance some critical metrics in particular at low supply voltages, by partitioning the arrays to balance the speed, the power consumption and the area, and also by adding some assist circuitries to speed up the access time and/or increase the yield."

　　As outlined in the paper, the Leti researchers took on these challenges with a CoolCube SRAM design focusing on the development of a compact and functional four-transistor bitcell, as well as reconfiguring memory between the CAM and SRAM according to the target application. Not only does the 4T SRAM bitcell becomes functional with 30 percent area reduction with respect to standard 6T bitcells, the reconfigurable CAM/SRAM outperformed state-of-the-art memories, with operations at 1.56GHz and 0.13fJ/bit energy per search.

　　In addition, memory was optimized using TFET, focusing on the exploitation of its negative differential-resistance effect to build ultralow-power SRAM, flip flops (FF) and refresh-free DRAM. Leti also developed a new compensation technique for crosspoint memory that reduces the voltage drop and leads to larger, cost-efficient memory arrays, while reducing the impact of temporal and spatial variations.

　　Since Monolithic 3D is an emerging technology, Giraud said preference was given to SRAM to minimize the risks. “However, as we found that 6T SRAM bitcell is not that suitable to achieve a significant area reduction, we decided to investigate the 4T bitcell," he said.

　　He said the reconfigurable CAM/SRAM appeared promising and clever by the close bitcell architecture between SRAM 6T and CAM. “Therefore, the 6T SRAM bitcell with two wordline signals and a virtual ground signal enables us to design the high-speed 6T-ReCAM/SRAM macrocell," he said.

　　The work from concept to the silicon measurement represents about one year of effort, said Giraud. The main challenge with the reconfigurable CAM/SRAM is to maintain good performance in both SRAM and CAM modes, which meant reducing the access time of the SRAM as well as minimizing the search time and the search energy of the CAM while using a regular 6T SRAM bitcell.

　　He said the “disruptive" TFET, owing to its differences to the MOS operation principle, is a promising candidate, not only to reduce leakage current and improve the sub-threshold slope, but also to present new features that would allow Leti to propose novel DRAM, SRAM and FF that clearly outperform state- of-the-art memories. Giraud said the TFET work exceeded their expectations thanks to the unique TFET property in reverse bias that they investigated for the first time. “We basically exploited the unipolarity of the TFET not as a drawback, but as an advantage," he said.

　　The emerging crosspoint architecture, meanwhile is an attractive solution to occupy a new spot in the memory hierarchy between DRAM and flash, said Giraud. But there are problems, he added, including sneakpath current and voltage drop.

　　Giraud said short-term applications include crossbar circuits for storage-class memory and flexible SOCs with SRAM/CAM re-configurability. In the long run, Leti's CoolCube technology will be able to deliver very high-density SRAM. He said enabling TFET-based DRAM and integrating TFET standard cells into CMOS designs will allow circuit designers to take advantage of the best features of both technologies.