MRAM Momentum Poised to Disrupt Memory Workhorses

　　Last year could be described as a tipping point for the magneto-resistive random access memory (MRAM) market. Up until then, Everspin Technologies was the only company shipping commerical MRAM products. But as Spin Transfer Technologies (STT) CEO Barry Hoberman is always quick to acknowledge, Everspin's success has helped to pave the way for other MRAM players.

　　The genesis of STT goes back as far as 2001 with technology originally developed from research conducted by New York University Professor Andrew Kent. STT was formed and incubated by Boston-based Allied Minds in 2007. In September 2016, the developer of orthogonal spin transfer MRAM technology (OST-MRAM) announced it had fabricated perpendicular MRAM magnetic tunnel junctions (MTJs) as small as 20nm at its development fab based at the company's headquarters in Fremont, Calif.

　　Since then, STT has delivered samples of its spin transfer torque MRAM to customers in North America and Asia, a milestone that's significant in that it's one of several emerging memories considered to be a next-generation candidate to replace DRAM and NAND flash, which face scaling challenges as the industry moves to smaller nodes. STT is one of a handful of firms developing MRAM, so the delivery of samples is an important proof point validating both MRAM in general, and STT's technology in particular.

　　EE Times recently spoke with Hoberman about the company's ramp up, and the opportunities for MRAM as more players go to market, including where it might be a viable replacement for incumbent technologies.

　　EE Times Memory Designline: What has been the response to your sampling program so far?

　　Barry Hoberman: We've sampled to a good range of customers and enough of them are large, well-established, highly credible evaluators of this kind of memory. Our goal in this sampling cycle was to produce complete memories that met a robust measure of reliability. We're excited to have circulated devices that everybody is coming back with and saying they are fully functional, they've met all of the specs that were offered, and they couldn't find any errors. That's a great door opener for us pushing into the next engagement with customers who now rightly recognize us a company that has got baseline third-generation pMTJ technology that we know how to craft into working memories.

　　EE Times: How have the challenges for developing MRAM commercially differed from other emerging memories?

　　Barry Hoberman: The thing that is really important to grasp about MTJs is that they have had for over 10 years of proven production and reliability capabilities as used in the read heads of disk drives. Three and four billion read heads per year incorporate MTJs. The problem with MRAM is figuring out how to integrate the MTJ into the CMOS flow, how to craft the MTJ performance characteristics into something that is compatible with memory, and then how to scale up the fabrication of the MTJs – rather than one per read head, something in the order of a billion per memory chip. Those are three main challenges. It's very different from the other new memory technologies such as phase change, resistive RAM and nanowire, where the physics of the technology are all completely new, and not proven in any kind of manufacturing chain, nor have any working industrial ecosystem supporting them.

　　EE Times: You've referred to competitors such as Everspin as fellow pioneers on the MRAM trail. How do you view their successes as you move forward with your own technology?

　　Barry Hoberman: It's a confidence builder all the way across the ecosystem — investors, customers, equipment providers.

　　EE Times: What is your sense of potential MRAM going forward?

　　Barry Hoberman: We're aware of four foundries that have third-generation pMJT-based MRAM on their roadmap to enter production in the second half of 2018 timeframe or relatively soon after. MRAM positions as this early stage as three technologies. One, as a replacement for the NVM space, primarily embedded NOR flash. There's also a horizon for it to act as replacement for conventional CMOS high-speed embedded SRAM. We think our technology better differentiates in that space. The third space is in DRAM replacement. That market is probably going to start a little bit lower density, and the uptake in the market is likely to be led by persistence characteristics that help particularly in storage applications.

　　EE Times: To date, a lot of adoption of MRAM has been around storage applications. Are there examples of emerging applications in other market segments?

　　Barry Hoberman: There's a couple place in mobile phones where they need static memories upwards of 200Mbs and when you try do that with SRAM, it's a real cost distortion. Going to lower cost static memory looks very desirable. Moreover, because it's in mobile, they're sensitive to power. And the conventional solution below 40nm is a massive power hog in terms of leakage. Replacing that SRAM with MRAM almost completely wipes out that leakage. There's also the challenge of protecting data in flight. There are places where they want to have high bandwidth, high speed data moving through a system while it's on its way to its permanent storage location. The fault conditions that can jeopardize data before it makes it to its final resting place where it's completely secured and confirmed is an issue, and MRAM looks to be the ideal solution to that problem.

　　EE Times: How has the more pervasive use of flash created opportunities for MRAM?

　　Barry Hoberman: Think of partitioning the storage in a solid-state drive into a large amount of storage that has the time characteristics of flash – some people call it micro-second class NVM – and a lesser amount of storage that's build around a high-speed, persistent type of memory technology – some people call it nanosecond NVM. When you hybridize the system around those two technologies, properly partitioned for cost, you get a performance multiplier in the random IOPs relative to a conventional flash-based SSD by about an order of magnitude improvement.

　　EE Times: The Internet of Things (IoT) is creating new ways of using existing memory technologies to address issues such as power consumption while requiring relatively low densities. How can MRAM play a role?

　　Barry Hoberman: If you want to look at a straight out, face-to-face comparison with the other alternatives that are looking at IoT such as phase change and resistive RAM, and also flash, they simply don't have the endurance characteristics to do any of the things that look like data logging functions, especially where there's data logging functions running off of a small battery.

　　EE Times: Beyond the commitments of the foundries, what do you see driving development of MRAM in the next 12 to 18 months?

　　Barry Hoberman: The first major foundry that drops this into a production product line and truly starts to ship it is going to turn a tornado in the industry. The semi-conductor industry really has to keep in mind that the workhorses for the last forty-plus years have been variations of three technologies – SRAM, DRAM, and flash and its progenitor technologies. This is going to be the first major high-volume thing. There have been some either niche-ness technologies such as FRAM and EEPROM and they have all suffered from their niche-ness. But when you drop in MRAM, the characteristics are such that it's really the first thing to enter the framework in forty to fifty years. That alone is huge.