EUV, 7-nm Roadmaps Detailed

　　Extreme ultraviolet lithography (EUV) is set to enable 10-nm and 7-nm process nodes over the next few years, but significant work is still needed on photoresists to enable 5-nm chips, according to an analysis released at the Industry Strategy Symposium here.

　　At the same time, EUV maker ASML announced that it shipped 10 EUV systems last year and will ship 20 to 22 more this year. The systems will have, or at least support, a 250-W laser light source needed to produce 125 wafers/hour.

　　“The main pieces for EUV at 7 nm are in place, and we will see some volume of wafers this year … but photoresist defects are still an order of magnitude too high for 5 nm,” said Scotten Jones, president of IC Knowledge.

　　The new and expensive systems, in development more than 20 years, help make the fine features needed for next-generation chips and reduce the time required to make them. They will first be used on logic chips such as microprocessors and later applied to DRAMs but are not needed by today’s 3D NAND flash chips, said Scotten.

　　“EUV provides a tremendous reduction in cycle time and edge placement errors … but not much cost reduction, at least initially. There are so many other benefits that even if the cost is neutral, it still makes sense.”

　　Jones expects that ASML will ship another 70 systems in 2019–2020. That’s enough to support production nodes that he detailed in the works at Globalfoundries, Intel, Samsung, and TSMC.

　　ASML has plans in place to increase uptime of the systems from about 75% today to 90%, a top concern for lithographers, said Jones. In addition, he expressed confidence that the company will release in time a pellicle needed to protect some EUV wafers from contamination.

　　To enable resists for 5 nm, “we have 12 to 18 months to make a big improvement. The industry will run lots of wafers next year, and that will help,” said Jones, estimating that fabs will make nearly 1 million EUV wafers in 2019, and 3.4 million by 2021.

　　ASML aims to boost the 145 wafers/hour throughput that it can get with its 250-W light source to 155 w/h in 2020. It has demonstrated a 375-W light source working in the lab, said Peter Jenkins, ASML’s vice president for corporate strategy and marketing, in a talk here.

　　The company’s pellicle passes through 83% of light today and withstands a 245-W light source over 7,000 wafer exposures. However, the most aggressive 7-nm nodes need a 90% transmission used with a 250-W or greater light source.

　　One of the most interesting parts of Jones’ talk was a detailed analysis of 10-, 7-, and 5-nm nodes. TSMC qualified last fall a 7-nm process that is ramping now using existing optical steppers. Globalfoundries will ramp a similar process later this year, he said.

　　Both companies plan to ramp early next year a second-generation 7-nm process using EUV to make contacts and vias, reducing 15 optical layers to five EUV layers. The process does not provide a shrink, but it shortens cycle times and does not need a pellicle.

　　GF announced last June its 2019 plan for 7 nm with EUV. “TSMC has privately told customers that they will do this, too,” said Jones.

　　Chipmakers will probably have to use 30-ml/cm2 doses of resists, higher than the 20 ml/cm2that they target. They also will likely have to use e-beam systems to insect masks for defects rather than more accurate actinic systems still in the works that look for defects using the same 13.5-mm wavelength as the EUV systems, said Jones.

　　In addition to the work with cuts and vias, GF, Samsung, and TSMC plan 7-nm variants that use EUV with a pellicle to make a first metal layer. These processes will provide a shrink and reduce 23 optical layers to nine EUV layers.

　　This is the approach that Samsung will use for its first 7-nm node, called 7LPP, due early next year. TSMC will call its version 7FF+ and ramp it in mid-2019, and GF will follow with its 7LP+ late next year, said Jones.

　　The 10-nm process that Intel is currently ramping using optical steppers offers similar density to what its rivals plan with their best 7-nm variants, said Jones. He expects that Intel will adopt EUV for a 10-nm+ upgrade in 2019.

　　Samsung and TSMC are already talking about 5-nm processes that could be available before the end of 2019. They could be the first to use EUV for 1D metal layers. The processes could use EUV to reduce up to five cut masks for FinFETs down to one cut mask if better resists emerge, he said.

　　Separately, Jenkins said that ASML completed the optics design for its follow on EUV systems supporting a high numerical aperture, and its overall design is “well along.” The company announced in late 2016 plans for the system that should be in volume production in 2024.

　　Although EUV is a big milestone for enabling the semiconductor industry to make smaller chips, it is not expected to disrupt existing markets for chipmaking equipment and gear. Fabs will continue to need lots of existing capital equipment and supplies in tandem with EUV for future process nodes, said Jones.