SiFive Preps RISC-V Cloud Service

　　SiFive will try to build an easier, cheaper, faster way to design chips with a new $50.6 million funding round that included Huami, the venture arm of China’s Xiaomi. The series C aims to bring the startup to profitability and establish a broad market for its RISC-V cores.

　　SiFive will release a cloud service for designing RISC-V cores this year. It will expand it into an SoC design platform next year with silicon blocks from partners, said Naveed Sherwani, an industry veteran named chief executive of SiFive last July after 10 years at Open Silicon.

　　At an event announcing the funding, Sherwani made several ambitious promises he said would amount to a revolution in SoC design.

　　“Today it takes 9-18 months to finish a chip. In 12-18 months we will release a system that takes besides the two-month’s fab time, just 15-20 days… today people take 30 days to validate RTL, but we will do it in less than 3-5 hours — this is my promise,” he said.

　　In addition, SiFive’s IP partners will provide blocks at low or no cost until an SoC is in production. Upfront charges for IP can amount to 35 percent of the cost of prototyping an SoC, as much as $5 million in some cases. SiFive aims to reduce those costs as much as 85 percent so users can prototype a chip for roughly $750,000, said Shafy Eltoukhy, who oversees SiFive’s partner program.

　　“Anyone with a Web interface will be able to design amazing chips and solve problems in their communities,” said Sherwani, vowing to make the service free for universities and developing countries.

　　Some of SiFive’s promises are “very ambitious,” said market watcher Linley Gwennap of the Linley Group. Speeding up the design process is good, but it doesn’t add differentiation, “so the value of this approach is unclear. Most SoC startups design the most crucial IP blocks on their chips to ensure differentiation,” he said.

　　Although SiFive may reduce upfront costs, “customers still have to pay for the IP later when they ship product, so the program doesn’t reduce IP cost, it just delays it,” he added.

　　It’s not yet clear where SiFive’s platform will get traction. The service could give the emerging class of crowdfunded hardware startups an alternative to using off-the-shelf chips. Existing chip designers might find the service useful in lowering costs for SoCs that don’t require custom features.

　　To date, a handful of established electronics companies such as Microsemi, Nvidia and Western Digital are adopting RISC-V. They see the free instruction set architecture and its growing set of open source implementations as a way to reduce costs of designing their own cores.

　　Startup Esperanto Technologies announced last fall it is developing a family of high-end processors with RISC-V. And Andes Technology is embracing RISC-V as an alternative to its proprietary cores.

　　The new funding round was a large one for SiFive. The company,founded in July 2016 by a team of Berkeley grad students and their advisor who designed the initial RISC-V cores, had raised $13.8 million to date.

　　Investors were led in the latest round by Chenwei, a China VC firm with a broad tech portfolio that includes investments with Sutter Hill Ventures, SiFve’s initial lead investor. Other new investors included SK Telecom, Huami, two unnamed semiconductor companies and Western Digital, an existing RISC-V user.

　　“A lot of the RISC-V revolution will happen in China and India,” said Stefan Dyckerhoff, a managing director at Sutter Hill Ventures.

　　Sherwani said the funds will help him double his team to about 100 people, hiring mainly engineers with a combination of silicon and software expertise. It will also pay for about a dozen tape outs he wants to do this year to verify partner IP.

　　The SiFive cloud service he aims to build will let users create SoCs by selecting pre-verified RISC-V cores and peripheral IP blocks. It will generate fab-ready files, generally shielding customers from the complex details of EDA flows.

　　The service also will support an app store of tools from SiFive and its partners. A basic version of the service for designing RISC-V cores could be available as early as September.

　　SiFive’s IP partner program, launched in August, includes a dozen generally small IP companies so far and is adding a new member about every two weeks.

　　They include Analog Bits, Dover Microsystems, FlexLogix, Rambus and UltraSoC. DSPs are among the holes it has yet to fill.

　　Much of SiFive’s work behind the scenes will be in creating templates for each block, building subsystems of multiple blocks and making sure each combination of blocks can work together.

　　Meanwhile the company is already logging revenues from licenses for a handful of RISC-V cores it has designed to date. SiFive’s first purchase order was issued in mid-2016 for a soft core that acts as a cache coherent block in a Microsemi design.

　　“This week we received a multimillion-dollar order for the program that uses that processor from SiFive,” said Ted Speers, a Microsemi fellow and a board member of the RISC-V Foundation.

　　Some see RISC-V upending the dominance of Intel and Arm in microprocessors. At a RISC-V event last fall, WD said it will standardize on RISC-V and someday ship as many as two billion cores a year embedded in its disk and solid-state drives.

　　“Based on how Linux went from enthusiast users to a major OS for the data center, I predict in 10 years we will see every data center processor and half of edge device processors use RISC-V. All the control points will be broken, so you can build an SoC any way you want, with any interfaces you want— this is the freedom RISC-V will bring by 2028,” said Zvonimir Bandic, a senior director at WD and a board member of the RISC-V Foundation.

　　“I’m concerned that the talk of RISC-V eventually dominating the data center and client computing distracts from the hard work that needs to be done in the interim,” said analyst Gwennap. “So far, RISC-V has been adopted only for deeply embedded cores and not for running application software,” he added.

　　While others such as Esperanto will go head-to-head with giants such as Intel, that is clearly not SiFive’s goal.

　　Some developers have been keen to get their hands on SiFive’s latest processor, because it is the first RISC-V chip capable of running Linux. At the event last week, the company did not even mention it had just shipped a few cases worth of developer cards with the chips.