IBM Claims Tape Density Record

Release time:2017-08-04
author:Ameya360
source:R. Colin Johnson
reading:1168

  IBM researchers have set a tape areal-density record of 201 gigabytes per square inch — 20 times the areal density of current commercial tape drives — enabling a single palm-sized cartridge to hold 330 terabytes of uncompressed data. IBM Research and Sony Storage Media Solutions, which developed the nano-grained sputtered tape used for the demonstration prototype, described the achievement in Tsukuba, Japan, today (Aug. 2) at The Magnetic Recording Conference (TMRC 2017).

  Tape was invented more than 60 years ago and has repeatedly been deemed obsolete, but it remains the dominant method for storing cold data — data that is infrequently accessed but must be maintained, such as tax documents and health care records. The Big Data era has seen a resurgence in popularity for tape, which is valued for its small size and low cost relative to other storage alternatives as well as for its ability to store not just backup and archival data, but also the massive sensor and transactional data streams going up to the cloud. Indeed, business at IBM's tape storage unit grew by 8 percent last year, according to Gartner Inc.

  An increase in areal recording density simply means that less space is needed to store massive amounts of seldomly accessed information. IBM has broken the areal density record for tape storage five times since 2006 (see table), with most of the breakthroughs ending up in commercial products. Although the IBM-Sony's demonstration at TMRC 2017 is a prototype, IBM suggested that a commercial product could arrive next year.

  Sony achieved nano-granularity by sputtering vertically oriented, 7-nanometer magnetic grains on a tape substrate topped with a protective layer and a permanent lubricant. IBM created signal-processing algorithms that use noise-predictive detection to enable a linear density of 818,000 bits per inch of tape using an ultra-narrow, 48-nm tunneling magnetoresistive head. The ultra-narrow tracks enable a thirteenfold increase in track density over IBM’s previous generation, to 246,200 tracks per inch with a bit-error rate of <1e-20, the researchers reported.

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IBM expands strategic partnership with Samsung to include 7nm chip manufacturing
IBM (NYSE:  IBM) today announced an agreement with Samsung to manufacture 7-nanometer (nm) microprocessors for IBM Power Systems, IBM Z and LinuxONE, high-performance computing (HPC) systems, and cloud offerings.The agreement combines Samsung’s industry-leading semiconductor manufacturing with IBM’s high-performance CPU designs. This combination is being designed to drive unmatched systems performance, including acceleration, memory and I/O bandwidth, encryption and compression speed, as well as system scaling. It positions IBM and Samsung as strategic partners leading the new era of high-performance computing specifically designed for AI.“At IBM, our first priority is our clients,” said John Acocella, Vice President of Enterprise Systems and Technology Development for IBM Systems. “IBM selected Samsung to build our next generation of microprocessors because they share our level of commitment to the performance, reliability, security, and innovation that will position our clients for continued success on the next generation of IBM hardware.”Today’s announcement also expands and extends the 15-year strategic process technology R&D partnership between the two companies which, as part of IBM’s Research Alliance, includes many industry firsts such as the first NanoSheet Device innovation for sub 5nm, the production of the industry’s first 7nm test chip and the first High-K Metal Gate foundry manufacturing. IBM’s Research Alliance ecosystem continues to define the leadership roadmap for the semiconductor industry.“We are excited to expand our decade-long strategic relationship with IBM with our 7nm EUV process technology,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “This collaboration is an important milestone for Samsung’s foundry business as it signifies confidence in Samsung’s cutting-edge high performance EUV process technology.”Samsung is a member of the OpenPOWER Foundation, a vendor ecosystem facilitating the development of IBM Power architecture-based customized servers, networking and storage for future data centers and cloud computing. Samsung is also a member of the Q Network to help advance the understanding of applications software in quantum computing for the industry.
2018-12-21 00:00 reading:2833
With Alkaline Chemistry, Copper Could Be Forever
IBM shook the foundations of next-generation semiconductor-node planning when it asserted last month that copper would remain the interconnect of choice at 5 nanometers and below. Today (Dec. 12), Aveni (Massy, France) sought to drive a nail in the coffin of copper alternatives by demonstrating that replacing acid-based processing chemistries with an alkaline alternative can easily extend copper to the 3-nm node and quite possibly to the end of the road for complementary metal-oxide semiconductor (CMOS) technology.Today’s copper dual-damascene interconnects are accompanied by a tantalum nitride (TaN) copper diffusion barrier and cobalt liner. As copper wires get thinner, acidic copper chemistries can etch through the liner, enabling the copper plating to interact with the underlying TaN film. The resultant formation of tantalum oxides can create random open circuits that reduce production yields. Semiconductor companies therefore have explored replacement options such as solid cobalt, ruthenium, graphene, and even carbon nanotubes.Aveni claims its back-end-of-line alkaline electroplating chemistry makes a switch from copper unnecessary because it leaves the cobalt layer untouched. “One of the problems with acidic chemistries is that they often etch through to the underlying barrier layer. With alkaline chemistry, you do not have this underlay-etching problem,” Aveni CTO Frédéric Raynal told EE Times in an advance interview.Raynal said acidic chemistry molecules are much larger than the molecules in the alkaline chemistry Aveni uses for its Sao-branded process. The large molecules inhibit acidic chemistries’ utility at or below the 40-nm pitches used for designs with aggressive design rules (10 nm and below). Whereas acidic chemistries are challenged to fill the advanced features of lower-level metal layers, such as Metal 1 through Metal 4, alkaline chemistries can be effectively employed for those layers, according to Aveni.“To our knowledge, we are the only successful supplier of alkaline chemistries,” Raynal said. The company claims to be working with all of the semiconductor makers prototyping 5-nm chips except Intel, which it hopes to recruit.Aveni promises to publish a paper fully explaining and quantifying its results in 2018.
2017-12-13 00:00 reading:1186
IBM Power 9 Servers Target AI
  IBM announced its first Linux servers to use its Power 9 processors, targeting businesses that want to accelerate machine learning jobs. The systems are the first to use PCI Express Gen 4 as well as NVLink 2.0 to attach Nvidia GPUs and IBM’s OpenCAPI for FPGAs and other accelerators.  The company claims it will approach the prices of rival x86 systems while delivering greater bandwidth. However, it’s unclear what accelerators will be available for the new interconnects.  The NVLink 2.0 attaches up to six Nvidia GPUs to a Power 9 system delivering 5.6 times the bandwidth of the PCIe Gen 3 links used on x86 server, IBM claimed. The additional bandwidth translates to about 3.7-times speed up on machine learning jobs using frameworks such as Chainer or Caffe, it said.  IBM provides optimized versions of AI frameworks that can distribute compute-intensive training jobs across hundreds of GPUs with 95 percent scaling, it added.  The company expects partners will provide FPGAs and NAND flash drives for its PCIe Gen 4 slots. It has demonstrated systems with the Mellanox Innova 2 Ethernet/FPGA card which has not yet announced its general availability date.  Xilinx has a prototype FPGA working on the OpenCAPI link. The interface is based on standard serdes to ease porting for logic chips as well as future storage-class memories, however, IBM gave no other examples of chips planned for the interconnect.  “I think IBM will continue to face issues of ecosystem support. They have Nvidia, but I haven’t seen a whole lot of people rushing to OpenCAPI,” said Nathan Brookwood, principal of market watcher Insight64.  “In servers, it’s still Intel’s party, and it’s been hard for anybody else to crash that party. It’s much easier for someone like AMD. You don’t have to change a line of software as opposed to IBM and ARM servers that require software changes that are always problematic,” Brookwood said.  “IBM is clearly the first to use PCI Express Gen 4, but I don’t know if that’s going to make a huge difference in this generation, and next year others will be there too. So, it’s hard to see how they will make much progress against the Intel juggernaut,” he added.
2017-12-06 00:00 reading:1117
IBM: Copper Interconnects Here to Stay
  When aluminum interconnects became too slow for complementary metal oxide semiconductors (CMOS) at the 180 nanometer node, IBM led the way to the now universally used copper interconnects starting in 1997.  Now, on its 20th anniversary, many other interconnects are being proposed to replace copper, notably graphene. IBM, however, claims that slight tweaks to copper deposition will give it an enduring edge all the way to the end of the road for CMOS.  Big Blue is touting "copper forever" at the IEEE Nanotechnology Symposium this week in Albany, with more details expected to be revealed at the IEEE International Electronic Devices Meeting (IEDM) in San Francisco.  "Graphene is not readily manufacturable, and furthermore end-to-end comparisons show graphene does not flow uniformly and can't achieve the low resistances of enhanced copper interconnects," IBM Fellow Dan Edelstein told EE Times in an exclusive preview of his Nanotechnology Symposium talk.  "Copper with a thin cap of cobalt is better than graphene at carrying current and even at the smallest sizes imaginable copper interconnects are still the best solution, perhaps with cobalt, nickel, ruthenium or another platinum-group noble metals brought in to underlay it," Edelstein said.  Initial IBM studies showed that copper had 40 percent less resistance than aluminum, resulting in an immediate 15 percent burst in processor speeds. Plus, copper is more durable and 100 times more reliable, according to IBM.  But the industry in the 1990s expressed two big resistances to the changeover to copper — both surmounted by IBM. The first was the fact that copper "poisons" silicon when it comes into direct contact. That was solved by encasing copper in tantalum-nitride and tantalum in a diffusion barrier all around.  The second was its deposition method. Aluminum was previously fabricated as interconnects by depositing an even layer on a topping of dielectric with vias down to the silicon, after which it was etched. Since copper had to be encased in the tantalum compound, this substrative method was not possible. Instead, IBM came up with an additive method with the kind of electroplating used for printed-circuit boards (PCBs).  Electroplating had never before been used on CMOS chips, so stumped the rest of the industry until IBM shared its discovery of it and the encasing process to prevent copper poisoning of the underlying CMOS circuitry. The most complicated part of the process, however, was the dual-damascene process of electroplating inside deep trenches, enabling from seven to 17 (then and today, respectively) metal layers to interconnect the single layer of silicon transistors on typical planar chip. And then there was the "magic."  "We discovered that copper's 'magic' was that in the process of preparing it, trace impurities vastly improved its reliability," Edelstein told EE Times. "Our electroplated copper had minimal electro-migration [the bane of interconnections in microelectronics] because of these traces of carbon, nitrogen, sulfur, chlorine and phosphorus, all of which were present in as little as 10 parts per million."  Cyprian Uzoh, the chemist on the team (whose name in his native Nigerian language means “copper”) came up with the electroplated copper "recipe" and said at the time of the impurities that "a little salt and pepper never hurt anybody."  "I firmly believe that the discovery of the superior, cheaper and easier interconnection of CMOS transistors with copper instead of aluminum resulted from IBM Research's multi-disciplinary expertise across chemistry, electrical engineering and physics," Edelstein told EE Times. "Plus, we built our own PCBs, chips and their packaging, which together gave us the expertise to discover how electroplating copper could replace aluminum. All our competitors sub-contracted many of these steps, putting IBM in the unique position to solve the puzzle."  The dual damascene process, for instance, essentially added silicon dioxide as insulation between layers while simultaneously permitting the tantalum-coated copper wires to be electroplated into the chips trenches. These techniques depended on multidisciplinary expertise, enabling IBM to produce the first prototypes in 1997 and the first production PowerPC chips in 1998. When compared to the previous generation 300-MHz PowerPCs, the 1998 versions experienced a 33 percent boost in speed attributable to their unique copper interconnect. And putting the rest of the industry on the trail to figure out how IBM was doing it.  "At first our competitors said that it would only last one generation, but so far it has lasted 12. And we believe that for CMOS it will last forever, except perhaps on the bottom layer next to the advanced node silicon transistors which may require cobalt, nickel, ruthenium or another platinum-group noble metals," Edelstein told EE Times.
2017-11-16 00:00 reading:1777
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