IBM Claims Tape Density Record-Ameya360 electronic components purchasing network

IBM Claims Tape Density Record

Release time：2017-08-04

author：Ameya360

source：R. Colin Johnson

reading：1170

　　IBM researchers have set a tape areal-density record of 201 gigabytes per square inch — 20 times the areal density of current commercial tape drives — enabling a single palm-sized cartridge to hold 330 terabytes of uncompressed data. IBM Research and Sony Storage Media Solutions, which developed the nano-grained sputtered tape used for the demonstration prototype, described the achievement in Tsukuba, Japan, today (Aug. 2) at The Magnetic Recording Conference (TMRC 2017).

　　Tape was invented more than 60 years ago and has repeatedly been deemed obsolete, but it remains the dominant method for storing cold data — data that is infrequently accessed but must be maintained, such as tax documents and health care records. The Big Data era has seen a resurgence in popularity for tape, which is valued for its small size and low cost relative to other storage alternatives as well as for its ability to store not just backup and archival data, but also the massive sensor and transactional data streams going up to the cloud. Indeed, business at IBM's tape storage unit grew by 8 percent last year, according to Gartner Inc.

　　An increase in areal recording density simply means that less space is needed to store massive amounts of seldomly accessed information. IBM has broken the areal density record for tape storage five times since 2006 (see table), with most of the breakthroughs ending up in commercial products. Although the IBM-Sony's demonstration at TMRC 2017 is a prototype, IBM suggested that a commercial product could arrive next year.

　　Sony achieved nano-granularity by sputtering vertically oriented, 7-nanometer magnetic grains on a tape substrate topped with a protective layer and a permanent lubricant. IBM created signal-processing algorithms that use noise-predictive detection to enable a linear density of 818,000 bits per inch of tape using an ultra-narrow, 48-nm tunneling magnetoresistive head. The ultra-narrow tracks enable a thirteenfold increase in track density over IBM’s previous generation, to 246,200 tracks per inch with a bit-error rate of <1e-20, the researchers reported.

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IBM: Copper Interconnects Here to Stay

　　When aluminum interconnects became too slow for complementary metal oxide semiconductors (CMOS) at the 180 nanometer node, IBM led the way to the now universally used copper interconnects starting in 1997.　　Now, on its 20th anniversary, many other interconnects are being proposed to replace copper, notably graphene. IBM, however, claims that slight tweaks to copper deposition will give it an enduring edge all the way to the end of the road for CMOS.　　Big Blue is touting "copper forever" at the IEEE Nanotechnology Symposium this week in Albany, with more details expected to be revealed at the IEEE International Electronic Devices Meeting (IEDM) in San Francisco.　　"Graphene is not readily manufacturable, and furthermore end-to-end comparisons show graphene does not flow uniformly and can't achieve the low resistances of enhanced copper interconnects," IBM Fellow Dan Edelstein told EE Times in an exclusive preview of his Nanotechnology Symposium talk.　　"Copper with a thin cap of cobalt is better than graphene at carrying current and even at the smallest sizes imaginable copper interconnects are still the best solution, perhaps with cobalt, nickel, ruthenium or another platinum-group noble metals brought in to underlay it," Edelstein said.　　Initial IBM studies showed that copper had 40 percent less resistance than aluminum, resulting in an immediate 15 percent burst in processor speeds. Plus, copper is more durable and 100 times more reliable, according to IBM.　　But the industry in the 1990s expressed two big resistances to the changeover to copper — both surmounted by IBM. The first was the fact that copper "poisons" silicon when it comes into direct contact. That was solved by encasing copper in tantalum-nitride and tantalum in a diffusion barrier all around.　　The second was its deposition method. Aluminum was previously fabricated as interconnects by depositing an even layer on a topping of dielectric with vias down to the silicon, after which it was etched. Since copper had to be encased in the tantalum compound, this substrative method was not possible. Instead, IBM came up with an additive method with the kind of electroplating used for printed-circuit boards (PCBs).　　Electroplating had never before been used on CMOS chips, so stumped the rest of the industry until IBM shared its discovery of it and the encasing process to prevent copper poisoning of the underlying CMOS circuitry. The most complicated part of the process, however, was the dual-damascene process of electroplating inside deep trenches, enabling from seven to 17 (then and today, respectively) metal layers to interconnect the single layer of silicon transistors on typical planar chip. And then there was the "magic."　　"We discovered that copper's 'magic' was that in the process of preparing it, trace impurities vastly improved its reliability," Edelstein told EE Times. "Our electroplated copper had minimal electro-migration [the bane of interconnections in microelectronics] because of these traces of carbon, nitrogen, sulfur, chlorine and phosphorus, all of which were present in as little as 10 parts per million."　　Cyprian Uzoh, the chemist on the team (whose name in his native Nigerian language means “copper”) came up with the electroplated copper "recipe" and said at the time of the impurities that "a little salt and pepper never hurt anybody."　　"I firmly believe that the discovery of the superior, cheaper and easier interconnection of CMOS transistors with copper instead of aluminum resulted from IBM Research's multi-disciplinary expertise across chemistry, electrical engineering and physics," Edelstein told EE Times. "Plus, we built our own PCBs, chips and their packaging, which together gave us the expertise to discover how electroplating copper could replace aluminum. All our competitors sub-contracted many of these steps, putting IBM in the unique position to solve the puzzle."　　The dual damascene process, for instance, essentially added silicon dioxide as insulation between layers while simultaneously permitting the tantalum-coated copper wires to be electroplated into the chips trenches. These techniques depended on multidisciplinary expertise, enabling IBM to produce the first prototypes in 1997 and the first production PowerPC chips in 1998. When compared to the previous generation 300-MHz PowerPCs, the 1998 versions experienced a 33 percent boost in speed attributable to their unique copper interconnect. And putting the rest of the industry on the trail to figure out how IBM was doing it.　　"At first our competitors said that it would only last one generation, but so far it has lasted 12. And we believe that for CMOS it will last forever, except perhaps on the bottom layer next to the advanced node silicon transistors which may require cobalt, nickel, ruthenium or another platinum-group noble metals," Edelstein told EE Times.

2017-11-16 00:00 reading：1781

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