[News] <span style='color:red'>Samsung</span> Fails to Secure Qualcomm’s 3nm Orders for the Coming Year, Dual Foundry Strategy Postponed
  According to TechNews’ report, TSMC and Samsung fiercely compete in the semiconductor foundry sector. Earlier market reports suggested that Qualcomm’s Snapdragon 8 Gen 4 mobile processor might adopt a dual-foundry strategy with TSMC and Samsung manufacturing simultaneously.  However, according to the latest industry information, due to Samsung’s conservative expansion plan for next year’s 3nm production capacity and unstable yields, Qualcomm has officially canceled the plan to utilize Samsung for next year’s processors. The dual-sourcing model is now postponed until 2025.  Samsung began mass production of its first-generation 3nm GAA (SF3E) process at the end of June last year, marking Samsung’s initial use of the innovative GAA architecture for transistor technology. The second-generation 3nm process, 3GAP (SF3), will utilize the second-generation MBCFET architecture, optimizing it based on the foundation of the first-generation 3nm SF3E. It is expected to enter mass production in 2024.  The dual-foundry strategy for Qualcomm was initially leaked by the reputable source Revegnus via the X platform (formerly Twitter). It was mentioned that the Snapdragon 8 Gen 4 processor would adopt TSMC’s 3nm (N3E) process, while Samsung’s 3GAP process would be used for the Snapdragon 8 Gen 4 supplying Samsung’s Galaxy series smartphones. Other sources suggested that due to limited capacity at TSMC’s 3nm production, Qualcomm had to seek Samsung as an alternative chip foundry.  As a result, Qualcomm originally anticipated dual-foundry production with both TSMC and Samsung in 2024, with hopes of being the first customer for the 3GAP process. However, considering Samsung’s conservative 3nm production capacity plan for next year and the instability in yields, Qualcomm decided to scrap the plan and exclusively rely on TSMC, pushing the dual-foundry strategy to 2025.  Currently, TSMC’s 3nm process technology capacity is on the rise, with expectations that by the end of 2024, monthly production capacity will reach 100,000 wafers, and the revenue contribution will increase from the current 5% to 10%.
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Release time:2023-12-01 14:48 reading:2015 Continue reading>>
IC Design Companies Seek Advanced Process Second Source, Overview of Competition Between TSMC and <span style='color:red'>Samsung</span>
  According to TechNews’ report, Apple, NVIDIA, AMD, Qualcomm, and MediaTek all utilize TSMC’s semiconductor processes for manufacturing their latest chips, with some potentially employing Samsung’s foundry, though typically not for flagship products.  With Samsung’s improved yield rates in recent months, the company is eager to secure a portion of the orders, particularly for the 3-nanometer GAA (Gate-All-Around) process.  Earlier market reports suggested that Qualcomm’s Snapdragon 8 Gen 4 might adopt a dual-foundry strategy, simultaneously utilizing TSMC’s N3E process technology and Samsung’s SF3E process technology.  However, both Qualcomm and MediaTek currently plan to employ TSMC’s second-generation 3-nanometer process technology (N3E) for manufacturing chips like the Snapdragon 8 Gen 4 and Dimensity 4, without pursuing a dual-foundry strategy at this time.  As of the end of June 2022, Samsung announced the commencement of production for 3-nanometer process chips at its Hwaseong Industrial Complex in South Korea. These chips incorporate a new GAA transistor architecture technology, rumored to be more energy-efficient compared to TSMC’s 3-nanometer FinFET technology. Despite this, in the realm of 3nm, Samsung has yet to secure substantial orders from major clients.  Interestingly, the company has seen more success in the 4nm domain. It is reported that Samsung has gradually addressed yield and various issues in the 4-nanometer process technology domain. The third generation of 4-nanometer process technology has seen improvements in performance, reduced power consumption, increased density, and achieved yields close to TSMC’s level. Market sources indicate that Samsung has gained recognition from companies like AMD and Tesla, securing new orders.  Currently, TSMC’s 3-nanometer process technology production capacity is ramping up, with an expected monthly capacity of 100,000 wafers by the end of 2024. The revenue contribution is projected to increase from the current 5% to 10%.  Meanwhile, Samsung plans to introduce the second generation of its 3-nanometer process technology, named SF3 (3GAP), in 2024. Building upon the existing SF3E, it aims for further optimization, and Samsung’s in-house Exynos 2500 is expected to be one of the first high-performance chips to adopt this new process technology.
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Release time:2023-11-27 13:51 reading:1743 Continue reading>>
Intense Competition in Advancing Processes at the 2nm by <span style='color:red'>Samsung</span>, Intel, and TSMC
  According to TechNews’ report, Gitae Jeong, Vice President of Samsung Electronics, recently revealed in an interview that the company is set to introduce the SF1.4 (1.4nm) process, expected to enter mass production in 2027.  This announcement intensifies the competition in advanced semiconductor manufacturing, particularly in the development of 2.5D/3D integrated heterogeneous structure packaging among the three major semiconductor foundry giants.  *TSMC: N3P Process Superior to Intel 18A, N2 to Lead Industry’s Advanced Processes  Previously, the semiconductor industry reported challenges with both TSMC and Samsung achieving yields above 60% for their 3nm processes due to undisclosed issues. TSMC’s yield was reported to be only 55%, below the normal yield rate.  However, TSMC’s President, C.C. Wei, expressed optimism, stating that current N3 demand is better than three months ago, contributing to a healthy growth outlook for TSMC in 2024.  Wei also anticipates that TSMC’s 3nm process will contribute a mid-single-digit percentage (4%-6%) to the company’s annual wafer revenue in 2023.  Regarding competition with rival Intel’s 18A process, Wei believes that TSMC’s N3P process offers better performance, power, and area (PPA), alongside improved cost efficiency and technical maturity. Furthermore, TSMC’s upcoming N2 process is expected to be the industry’s most advanced when introduced.  *Intel: Striving for the Fourth Customer for 18A Process Outsourcing Orders  Intel’s CEO, Pat Gelsinger, has revealed that the 18A process has secured orders from three customers and aims to acquire a fourth customer by the end of the year. The advanced 18A process is scheduled to begin production at the end of 2024, with one customer already having made an advance payment. External expectations suggest that the customer could possibly be NVIDIA or Qualcomm.  Intel has stated that Intel 4 and Intel 3 processes are similar, as are Intel 20A and Intel 18A processes. Consequently, Intel’s primary focus will be on offering Intel 3 and Intel 18A to semiconductor foundry customers. Meanwhile, Intel 4 and Intel 20A processes are more likely to be used internally. However, Intel is open to accommodating customer requests if they express interest in adopting these later processes.  *Samsung: Commencing Mass Production of SF2 in 2025, Prioritizing Internal Use  Due to challenges with the three-nanometer (3nm) manufacturing process, there have been reports that Samsung plans to shift directly to the more advanced two-nanometer (2nm) process.  According to Samsung’s Foundry Forum (SFF) plan, they will begin mass production of the 2nm process (SF2) in 2025 for mobile applications, expand to high-performance computing (HPC) applications in 2026, and further extend to the automotive sector and the expected 1.4nm process by 2027.  Similar to Intel, Samsung intends to prioritize the production of its own products using the 2nm process. The 2nm process products will initially be utilized for Samsung’s in-house products rather than external customer products.  *Summary  While TSMC’s N3 series currently enjoys broad support, including N3E, N3X, and N3P process series, the move to 2nm introduces new variables as it adopts a completely new GAAFET architecture. Regardless, whether it’s TSMC’s N2, Intel’s 18A, or Samsung’s SF2, each of them possesses its competitive strengths. The industry is also eagerly anticipating the future developments in advanced semiconductor processes.
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Release time:2023-11-03 14:50 reading:1450 Continue reading>>
Intel, <span style='color:red'>Samsung</span>, TSMC Race in Cutting-Edge Processes
  Driven by emerging technologies like AI and high-performance computing, the semiconductor foundry industry increasingly emphasizes the importance of advanced manufacturing processes. Recently, the industry has seen significant developments. Intel announced that it has commenced large-scale production of its Intel 4 process node, while TSMC and Samsung are equally committed to advancing their advanced process technologies.  Intel’s Mass Production of Intel 4 Process Node  On October 15th, Intel China’s official public account revealed that Intel has initiated large-scale production of the Intel 4 process node using Extreme Ultraviolet Lithography (EUV) technology. According to Intel, they are making significant progress with their “Four Years, Five Nodes” plan. This plan aims to produce next-generation products that meet the computational demands driven by AI’s role in the “Siliconomy.”  Being the first process node produced by Intel using EUV lithography technology, Intel 4 offers substantial improvements in performance, efficiency, and transistor density compared to its predecessors. Intel 4 was unveiled at the Intel Innovation 2023 held in September this year.  In comparison to Intel 7, Intel 4 achieves a 2x reduction in area, providing high-performance computing (HPC) logic libraries and incorporating various innovative features.  In detail, Intel 4 simplifies the EUV lithography process, optimizing it for high-performance computing applications, supporting both low voltage (<0.65V) and high voltage (>1.1V) operations. Compared to Intel 7, Intel 4 boasts more than a 20% improvement in iso-power performance, and high-density Metal-Insulator-Metal (MIM) capacitors deliver outstanding power supply performance.  Intel’s “Four Years, Five Nodes” plan is advancing with the following process updates:  Intel 7 and Intel 4 are currently in large-scale production. Intel 3 is on track to meet its planned target by the end of 2023.  Intel’s Intel 20A and Intel 18A, which use Ribbon FET all-around gate transistors and PowerVia backside power delivery technology, are also progressing well, with a target of 2024. Intel will soon introduce the Intel 18A process design kit (PDK) for Intel Foundry Services (IFS) customers.  With the adoption of Intel 4 process nodes, the Intel Core i9 Ultra processor, codenamed “Meteor Lake,” will be released on December 14th this year, ushering in the AIPC era.  On Intel 3 process nodes, the energy-efficient E-core Sierra Forest processor will be launched in the first half of 2024, and the high-performance P-core Granite Rapids processor will follow closely.  Samsung’s 2nm Process Detailed Production Plan  Samsung has already commenced production of its second-generation 3nm chips and plans to continue focusing on 2nm chips.  On June 28th, Samsung Electronics unveiled its latest foundry technology innovations and business strategies at the 7th Samsung Foundry Forum (SFF) in 2023.  In the era of artificial intelligence, Samsung’s foundry program, based on advanced GAA process technology, offers robust support for customers in AI applications. To this end, Samsung has disclosed a detailed production plan and performance levels for its 2nm process. The plan is to achieve mass production for mobile applications by 2025 and respectively expand to HPC and automotive electronics in 2026 and 2027.  Samsung reports that the 2nm process (SF2) improves performance by 12% compared to the 3nm process (SF3), increases efficiency by 25%, and reduces the area by 5%.  Furthermore, reports indicated that Samsung is ensuring the production capacity for products using the next-generation EUV lithography machine, High-NA, in September. This equipment is expected to have a prototype by the end of this year and officially enter production next year.  TSMC’s Mass Production of 2nm by 2025  This year, TSMC has unveiled its latest advanced semiconductor manufacturing roadmap in various locations, including Santa Clara, California, and Taiwan. The roadmap covers a range of processes from 3nm to 2nm.  TSMC’s current roadmap for 3nm includes N3, N3E, N3P, N3X, and N3 AE, with N3 serving as the foundational version, N3E as an enhanced version with further cost optimization, N3P focusing on improved performance with a planned start in the second half of 2024, N3X targeting high-performance computing devices with a mass production goal in 2025, and N3 AE designed specifically for the automotive sector, offering greater reliability and the potential to shorten time-to-market by 2-3 years.  In the 2nm realm, TSMC is planning to achieve mass production of the N2 process by 2025. TSMC has reported that the N2 process will offer a 15% speed improvement over N3E at the same power or a 30% reduction in power consumption, with a 15% increase in transistor density. In September, media reports revealed that TSMC has formed a task force to accelerate 2nm pilot production and mass production, aiming for risk production next year and official mass production in 2025.  To ensure the smooth development of 2nm process technology, TSMC has initiated efforts in the upstream equipment sector. On September 12th, TSMC announced the acquisition of a 10% stake in IMS Nanofabrication, a subsidiary of Intel, for a price not exceeding $432.8 million. IMS specializes in the research and production of electron beam lithography machines, which find extensive applications in semiconductor manufacturing, optical component manufacturing, MEMS manufacturing, and more. The industry sees TSMC’s IMS acquisition as vital for developing crucial equipment and meeting the demand for 2nm process commercialization.
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Release time:2023-10-18 13:12 reading:1407 Continue reading>>
 TSMC’s 3nm Wins Big Qualcomm 5G Deal, Outshines <span style='color:red'>Samsung</span>, Intel
  According to a report from Economic Daily, TSMC’s 3-nanometer technology has attracted another heavyweight client. Following Apple and MediaTek, it is rumored that Qualcomm will also commission TSMC to produce its next-generation 5G flagship chip using the 3-nanometer process. The chip is expected to be unveiled in late October, making Qualcomm the third client for TSMC’s 3-nanometer technology.  In response to these rumors, Qualcomm has not provided any comments, while TSMC has chosen to remain silent. Industry experts speculate that TSMC’s 3-nanometer technology will likely attract additional orders from major players such as NVIDIA and AMD in the future. With various leading-edge fabs continuously seeking TSMC’s services, it appears that TSMC’s 3-nanometer technology remains the top choice for international giants.  Last year, Qualcomm unveiled its annual 5G flagship chip, the “Snapdragon 8 Gen 2,” manufactured using TSMC’s 4-nanometer process. The previous-generation Snapdragon “8 Gen 1” was produced using Samsung’s 4-nanometer process, but it encountered issues related to heat dissipation. Consequently, Qualcomm released an upgraded version, the “Snapdragon 8+ Gen 1,” using TSMC’s 4-nanometer process.  Qualcomm has traditionally adopted a multi-supplier strategy for semiconductor manufacturing. It is rumored in the industry that Qualcomm has privately informed its smartphone brand customers about the upcoming next-generation 5G flagship chip, the “Snapdragon 8 Gen 3,” expected to be announced in late October. This chip will be available in two process versions: TSMC’s 4-nanometer (N4P) and 3-nanometer (N3E).
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Release time:2023-09-26 14:52 reading:1567 Continue reading>>
<span style='color:red'>Samsung</span> cuts NAND flash memory production
Ameya360:Ambarella Selects <span style='color:red'>Samsung</span>’s 5nm Technology for Automotive AI Controller
  Samsung Electronics Co. Ltd’s Foundry business is providing its 5nm process technology to and Ambarella Inc. for its newly announced CV3-AD685 automotive AI central domain controller. This collaboration will help transform the next generation of autonomous driving vehicle safety systems by bringing new levels of AI processing performance, power and reliability.  The CV3-AD685 is the first production version of Ambarella’s CV3-AD family of automotive AI central domain controllers, with Tier-1 automotive suppliers announcing they will offer solutions using the CV3-AD system-on-chip (SoC) product family. Samsung’s 5nm process technology is optimized for automotive-grade semiconductors, with extremely tight process controls and advanced IP for exceptional reliability and outstanding traceability.  Ambarella will rely on Samsung’s 5nm process maturity and the technology’s solid track record. This 5nm process is backed by the company’s extensive experience in automotive foundry process, IP, and service package development to enable manufacturers to create cutting-edge innovations in assisted and automated mobility.  “Ambarella and Samsung Foundry have a rich history of collaboration, and we are excited to bring their world-class 5nm technology to our new CV3-AD685 SoCs,” said Fermi Wang, President and CEO at Ambarella. “Samsung’s proven automotive process technology allows us to bring new levels of AI acceleration, systems integration and power efficiency to ADAS and L2+ through L4 autonomous vehicles.”  The CV3-AD685 integrates Ambarella’s next-generation CVflow AI engine, which includes neural network processing that is 20 times faster than the previous generation of Ambarella’s CV2 SoCs. It also provides general-vector and neural-vector processing capabilities to deliver the overall performance required for full autonomous driving (AD) stack processing, including computer vision, 4D imaging radar, deep sensor fusion and path planning.  “Samsung brings 5nm EUV FinFET technology to automotive applications for unprecedented ADAS and vision processor performance,” said Sang-Pil Sim, executive vice president and head of Foundry Corporate Planning at Samsung Electronics. “With Tier-1 automotive suppliers already adopting the technology, we believe other automotive companies will also consider using the Ambarella CV3-AD SoC product family manufactured in Samsung’s 5nm process.”  The CV3-AD685 will be the first in the CV3-AD product family to use Samsung’s 5nm process, and this SoC integrates advanced image processing, a dense stereo and optical flow engine, ARM Cortex A78AE and R52 CPUs, an automotive GPU for visualizations, and a hardware security module (HSM). It features an “algorithm first” architecture that provides support for the entire autonomous-driving software stack.  The high-performance, power efficient and scalable CV3-AD family, which is built specifically for ADAS, complements a wide range of solutions for assisted driving, while advancing vehicle automation. The integrated CV3-AD685 SoC enables information from various sensors to be fused for robust L2+ to L4 autonomous driving. Samsung Foundry’s industry-leading process technology and advanced 3D-packaging solutions are powering many of the latest mobile, HPC and automotive solutions.  Samsung’s 5nm process is also backed by the Samsung Advanced Foundry Ecosystem (SAFE) program. The SAFE program ensures close collaboration between Samsung Foundry, ecosystem partners, and customers to deliver robust SoC designs based on certified key design components including Process Design Kits (PDK), reference flows with Design Methodologies (DM), a variety of Intellectual Properties (IP), and on-demand design support.
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Release time:2023-02-23 16:08 reading:3178 Continue reading>>
<span style='color:red'>Samsung</span> is developing next-generation memory chips for large-scale AI applications such as ChatGPT
  The large-scale application of ChatGPT and other AI chatbots will not only improve the application experience of introducing related technologies, but also bring new development opportunities to several fields, memory chip is one of them. Ameya360 reports that Samsung Electronics is exploring business opportunities by developing customized next-generation memory chips for large AI applications, such as ChatGPT, which is gaining popularity around the world.  The actual impact of ChatGPT on the chip circuit is mainly shown as follows: ChatGPT is based on Transformer technology. With the continuous iteration of the model and the increasing number of layers, the demand for computing power is increasing. Secondly, the three conditions for the operation of ChatGPT, namely, training data + model algorithm + computing power, require large-scale pre-training on the basic model. After three iterations of ChatGPT, the number of references increased from 117 million to 175 billion, and the amount of training increased significantly.  The New Computing business team of Samsung's memory business division is developing a customized next-generation memory for large-scale AI related to ChatGPT. The new computing business team, headed by Kim Jin-hyeon, is known to be a pioneer In the development of a business within the storage business division. Previously, the team focused on the development of Processing In Memory; PIM). Pims can not only store data, but also integrate and calculate data in memory, which can improve the efficiency of data processing and power consumption. Therefore, PIMs are suitable for AI.  In addition, some semiconductor industry insiders pointed out that although traditional AI chips occupy the mainstream at present and AI-dedicated chips are booming, they have met their physical limits, and the future of AI chips may be quantum chips.  Park Seong-soo, a senior researcher at the Quantum Technology Research Center at the Electronics and Communications Research Institute, said ChatGPT can also be used with a lot of computing resources, but if combined with future quantum computers, it will become a more intelligent artificial intelligence.  According to Gartner's report, total global semiconductor revenue in 2022 was approximately $601.7 billion, an increase of 1.1% year-on-year. Samsung's market share was 10.9 per cent. The ChatGPT scandal has created a new opportunity for Samsung to develop memory chips.
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Release time:2023-02-21 11:26 reading:3692 Continue reading>>
<span style='color:red'>Samsung</span> Electronics Establishes LCA Verification on Product Carbon Footprint of Its Semiconductor Business
  Samsung Electronics Co. Ltd’s Life Cycle Assessment (LCA) on the product carbon footprint of its semiconductor business has achieved verification from DNV.  LCA is a methodology for assessing environmental impacts throughout the lifecycle of commercial products, processes, or services, by quantifying the amount of energy, materials, and waste discharge. In detail, on its semiconductors’ carbon footprint, Samsung’s LCA covers raw material extraction to chip manufacturing, assembling, and testing. Its results are in accordance with ISO 14040, ISO 14044 and ISO 14067 to ensure credibility and transparency.  The carbon footprint is commonly used by Samsung and its customers to recognize the environmental impact across all phases of Samsung’s semiconductor products, and can be used as a metric to track and reduce carbon emissions.  “Since 2019, we have been actively mobilizing efforts to measure and reduce the carbon emissions of our key memory and logic solutions,” said Dooguen Song, Executive Vice President of the Environment, Health and Safety (EHS) Center at Samsung Electronics. “By leveraging LCA, we will be able to support our customers to achieve their carbon neutrality, as well as becoming more transparent on the environmental impact of the semiconductors we produce worldwide.”  “As a global expert in energy and environmental certification, DNV is pleased to have partnered with and to congratulate Samsung on successfully establishing its reliable LCA.” said JangSup Lee, CEO of DNV Business Assurance Korea. “Together with global business leaders like Samsung, we will continue to take part in creating a more sustainable environment in the future.”  Since 2019, 37 of Samsung’s semiconductor products received carbon footprint accreditation from the Carbon Trust and UL, 6 of its memory products certified for carbon reduction from Carbon Trust. Samsung’s eco-conscious product portfolio includes DRAM, SSD, embedded storage, mobile SoC, mobile Image Sensor, automotive LED packages.  Leveraging its LCA established at the end of last year, Samsung will quantify the carbon footprints of chips manufactured across all of its global manufacturing, testing and assembly locations in Korea, China, and the U.S.  With sustainability at its core, Samsung will expand its LCA to include water and resource footprints to provide a more comprehensive assessment that will ultimately reduce the environmental impact of various applications such as mobile and wearables, data centers, consumer electronics, automotive, communications and more.
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Release time:2023-02-13 15:12 reading:3242 Continue reading>>
<span style='color:red'>Samsung</span>, Micron Battling for NAND Supremacy
  Samsung Electronics and Micron Technology continue to fight for supremacy in the NAND market, with both companies recently announcing higher-density 3D NAND solutions—albeit with different nomenclatures.  Samsung has opted to focus on 3D NAND bit density with the introduction of its 1-terabit (Tb) triple-level–cell eighth-generation vertical NAND (V-NAND), which the company claims is the industry’s highest bit density. Meanwhile, Micron has opted to present its latest 3D NAND in term of layers, having announced its 232-layer 3D NAND mid-year in 2022.  Samsung’s eighth-gen V-NAND  SungHoi Hur, executive vice president of flash product and technology at Samsung, told EE Times during an interview that the company achieved high bit density through a Cell-on-Peri (COP) structure, which the company introduced with its seventh-generation V-NAND.  With a COP structure, a cell array area is placed above the peripheral. But even with a COP structure, part of the peripheral is placed outside of the cell, Hur said, meaning the cell array must be reduced along with the peripheral area below and next to the cell array to reduce chip size.  Samsung first introduced its vertically stacked V-NAND flash in 2013. “Since then, we have been developing disruptive technologies to reduce the area and height of cells and have accumulated a great deal of Samsung know-how,” Hur said.  That know-how includes Samsung’s high-aspect–ratio contact etching technology, which the company uses to reduce the area of the cell array. For the eighth-generation V-NAND, Samsung successfully minimized the area of all three parts from the previous generation to enable even more density, Hur added.  A specific challenge that Samsung aims to address is avoiding the cell-to-cell interference that normally occurs with scaling down if the mold of the cell unit gets slimmer for scaling. “To counteract that interference, we have identified possible tradeoffs in performance first; then we moved on to solving the fundamental problems,” Hur said.  He also noted that the purpose of Samsung’s solution was to develop an optimal operation scheme for minimizing interference during writing, applying a new material to the blocking layer in the cell to prevent electrons from bouncing out of the charge trap layer (CTL) due to voltage and improving the structure of the CTL.  Hur said reaching this milestone means overcoming a variety of hurdles. From a structural perspective, the molds could lean to one side more easily as the total stack height continues to grow. “As the cells become closer and smaller, we have to fight with decreasing cell current as well as interference among cells,” he said. Samsung is working to lower the total stack height by leveraging the support structure used in its seventh-generation V-NAND and the multi-hole technology while also exploring new solutions, including an innovative cell structure using new materials.
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Release time:2023-01-12 10:40 reading:3300 Continue reading>>

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