A startup emerged from stealth mode with a low-cost approach to building 2.5-D chip stacks that targets the Internet of Things. zGlue developed a substrate that can link more than a dozen die as an alternative to designing a more expensive and time-consuming SoC or a much larger circuit board.
“It takes too much time to customize chips today,” said Ming Zhang, founder and CEO of zGlue.
“I wanted to enable chips useful for a large IoT market, including many who may not understand things like timing closure and through silicon vias,” said Zhang, a veteran circuit design who worked on Intel Xeon and Samsung Exynos processors.
The startup is one of many companies using novel packaging to make up for the increasing complexity and cost of CMOS scaling. To date, most chip stacks have been too expensive for anything but the most high performance devices, but many companies are working on lower cost options.
zGlue uses a trailing-edge interposer of 24 to 48 mm2 with integrated passives as well as a controller supporting power management and security. Its chip-to-chip interface can be configured in software and can accommodate most packages but is optimal for WLCSPs.
The interposer supports up to 3,000 programmable interconnect pins. SPI and GPIO interfaces can run at up to 100 MHz and UART and I2C interfaces at lower rates. It supplies power to chip-lets at 1.8V and 3.3 V by default, adjustable to 100 mA max current.
“The interposer takes care of all system functions beyond what the chip-lets are doing…[and it supports] multiple power rails to MCUs and sensors…and absorbs into the substrate PMICs you would otherwise have to buy. Users can turn off or on functions based on their needs such as encrypted interconnects, anti-tampering checks and a transaction security engine,” Zhang said.
The approach is optimal for devices that would use at least four chips and probably no more than 30. “We can comfortably address a normal spectrum of system complexity for AR/VR, industrial and medical systems,” he said.
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