Chip Execs More Bullish on EUV

　　Chip executives are increasingly optimistic the industry will adopt extreme ultraviolet lithography and multibeam mask writers, according to a pair of surveys announced today. The new systems will help drive advances at a time when it’s becoming increasingly complex and expensive to make leading-edge devices.

　　Seventy-five percent of a survey of 75 semiconductor luminaries said they expect EUV will be adopted in high volume manufacturing before 2021. Only 1 percent said EUV will never be embraced, down from 6 percent last year and a whopping 35 percent in 2014.

　　“There’s no question in my mind,” EUV will be adopted starting with 7nm+ processes in the next few years, said Aki Fujimura, an industry veteran and spokesman for the eBeam Initiative, a trade group that conducted the survey over the summer.

　　Intel, Samsung and TSMC made multi-billion-dollar investments in EUV developer ASML which in turn bought light-source maker Cymer, driving the complex and expensive technology forward. “Over the last couple years, the problem got bad enough with 7 and 5nm that everyone finally said we got to make this work or the entire industry’s in trouble,” said Fujimura, who is chief executive of D2S, a maker of systems that use GPUs to accelerate mask defect repair.

　　The shift won’t be easy. Chip makers are expected to launch 7nm processes with existing immersion steppers, then migrate some steps to EUV later to reduce the need for multi-patterning.

　　“EUV is so novel and requires so much investment in the machine and ecosystem to support it that you can’t have a stepwise introduction. You have to introduce it more gradually than that …[and not] ask EUV to do its best right off the bat,” said Fujimura who is on his third startup after a career in EDA that started in 1979 and included two tours at Cadence Design Systems.

　　Over the past 12 months, mask makers created 1,041 EUV masks, up from 382 a year ago. EUV mask yields were only 64.3 percent, compared to 94.8 percent for all 462,792 masks exposed in the period, according to a separate survey of ten top mask makers.

　　“I attribute [the low figure] to startup yields…One might say it’s surprising it’s as high as 64.3 percent,” he said.

　　The chip execs were also bullish that multi-beam mask writers will see use in high volume manufacturing by the end of 2019, about a year later than they predicted in a 2016 survey. This year’s survey suggested existing variable shaped beam (VSB) mask writers will see longer use than expected.

　　The shift comes a time when mask sets and thus costs are still rising dramatically at leading-edge nodes. However, the survey of mask makers reported write times are generally stable.

　　Mask write times are “under control” in part because the latest VSB systems deliver up to 1,200 Amps/cm2, Fujimura said. However increasing data sets and defects are stretching out mask turnaround times for finer nodes. “Mask cost is increasing per critical layer and the number of masks is getting very high,” he said.

　　Indeed, respondents said 7-10nm nodes have 76 masks on average with a maximum of 112 masks reported by one company. That’s up from an average of 50 masks for the last planar node at 20nm and 25 masks at 130nm.

　　“More than 100 is clearly ridiculous,” he said. “We’ll see what happens with EUV” which requires fewer masks than immersion steppers, but the EUV masks are more complex and thus expensive to make, he added.

　　Meanwhile mask turnaround time for 7-10nm processes has stretched out to an average of 12 days, the survey said. That’s in part because it now takes about 21 hours on average for data preparation.

　　In addition, mask process correction (MPC) is now becoming a routine requirement as chips approach 7nm. The step takes an additional 21 hours on average, according to the survey. “MPC is exploding. Adding this extra step introduces extra run time,” Fujimura said.