RISC-V Spins into Drives, AI

　　Storage giant Western Digital announced that it will standardize on RISC-V processors and has invested in Esperanto Technologies, a startup designing high-end SoCs and cores using the open-source instruction set architecture. The two moves suggest that RISC-V has emerged as a viable — but not yet mature — alternative to ARM and the x86.

　　Long-term, WD expects that it could ship as many as 2 billion RISC-V chips a year inside its hard-disk and solid-state drives. Privately, the company also revealed that it is working on machine-learning accelerators for inference, probably related to its unspecified investment in Esperanto.

　　For its part, the startup tipped plans for a family of 64-bit RISC-V chips that will include:

• An AI “supercomputer-on-a-chip” to be made in TSMC’s 7-nm process.

• A 16-core “ET-Maxion” targeting highest single-thread performance

• A 4,096-core “ET-Minion” targeting performance-per-watt with a vector floating-point unit in each core.

　　“Having a major company like WD bet on the architecture is a huge boost for the RISC-V ecosystem, and having a startup try to take it to high-end products is a big deal because to date, RISC-V has been mainly in low-end microcontrollers for the IoT,” said Linley Gwennap, principal of market watcher The Linley Group.

　　Esperanto has kept a tight lid on its plans to date, although its chief executive, microprocessor veteran David Ditzel, has been a fixture at RISC-V events for some time. Ditzel designed server processors at the former Sun Microsystems and startup Transmeta before doing a relatively short stint at Intel.

　　“I wasn’t going to do something unless it could be bigger than Transmeta — its get big or go home,” said Ditzel in an interview.

　　He declined to describe details of his products, their architecture, or even the company’s funding. However, he did give a few examples of his team, which includes Tom Riodan, a former Intel and MIPS processor designer who sold his startup QED to PMC Sierra.

　　“He was going to start his own RISC-V company, but we got together instead,” said Ditzel.

　　In addition, the startup snagged “a chief architect of the Sony Playstation 3. He was about to start work on the PS5, and when he heard about what we are doing, he said he wanted to join.”

　　Advisors include Berkeley professor emeritus David Patterson, who helped launch RISC-V, and Alan Eustace, a veteran senior engineer at Google, HP, and Digital Equipment. Although Ditzel declined to give numbers, the startup has engineers in Silicon Valley and Europe, at least 27 of whom will attend this week’s RISC-V workshop.

　　Esperanto’s staff includes former Intel specialists in floating-point and out-of-order design as well as circuit designers and physical layout experts. A compiler team already wrote a shader compiler to run high-end graphics jobs on its chips.

　　At a RISC-V workshop here, Esperanto will demonstrate RTL, presumably running in an FPGA, handling neural-networking jobs such as image recognition. The company’s general-purpose processors haven’t taped out yet but will target a range of applications.

　　“Top of our apps list is training and inference; we can do pretty good at graphics for high-end VR/AR … [the architecture] works best for problems with lots of parallelism,” said Ditzel.

　　The chips will use 16-bit floating point for training but support lower bit widths and integer operations for neural nets, too. “We will have more performance and fewer watts than competitors and more scalable power — most other [training] chips are hot — we can do lower-power apps as well.”

　　Unlike training accelerators from rivals such as Nvidia, Intel, and startup Graphcore, “we’re not at a max reticle die size,” he said of the 7-nm chip.

　　One of the company’s early targets may be embedded processors for devices such as Amazon Echo or Google Home. Time-to volume was one lesson from his startup Transmeta, said Ditzel, leading to a strategy of “being able to start in broad consumer spaces rather than day-one in servers” where design cycles can span two years.

　　The startup’s main business will be selling SoCs; however, it also may sell systems using them. In addition, it is open to licensing its cores “to make RISC-V more widespread.”

　　The relative immaturity of RISC-V and software for it is a chief challenge today.

　　“The GCC compiler is pretty stable and Linux ports are being upstreamed, but LLVM still has ways to go,” said Ditzel. “By the time we are selling chips, there will be a lot more maturity. There hasn’t been much silicon until recently with the SiFive parts, but once that’s there, the software will come along.”

　　“We are in it for the long haul … this is about the next six years, not the next six months.”

　　Along the way, Esperanto expects to take a lead role in defining extensions to the RISC-V instruction set. The company employs the co-lead of the foundation’s working group on a vector architecture, and Ditzel led work on extensions to Sun’s Sparc CPU back in the day.

　　For its part, Western Digital plans to transition “future core, processor, and controller development” to RISC-V. It currently consumes more than a billion cores a year. It has been a member of the RISC-V Foundation from the outset but has said little about its plans previously.

　　“The open-source movement has demonstrated to the world that innovation is maximized with a large community working toward a common goal,” said Martin Fink, WD’s CTO in a press statement.

　　“For that reason, we are providing all of our RISC-V logic work to the community,” said Fink, who was slated to keynote the event this week. “We also encourage open collaboration among all industry participants, including our customers and partners, to help amplify and accelerate our efforts. Together, we can drive data-focused innovation and ensure that RISC-V becomes the next Linux success story.”

　　In an FAQ, the company said that it has no plans to make merchant semiconductors. It positioned the move as an extension of its storage business rather than a replacement of it.